1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor apparatus.
2. Description of Related Art
A vertical power MOSFET for applying a current vertically to a surface of a semiconductor substrate is widely known as a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) for high pressure. Demands for such a power MOSFET has been increasing in recent years along with rapid expansion of mobile device and advance in communication technology. Further, a technology to reduce manufacturing cost of a power MOSFET without affecting a performance of the power MOSFET is desired.
Examples of gate structures of a vertical power MOSFET includes a planar gate structure whereby a planar gate electrode is provided over a surface of a semiconductor substrate, and a trench gate structure whereby a gate electrode is provided in a trench vertical to the surface of the semiconductor substrate.
A manufacturing method of a power MOSFET having a planar gate structure is disclosed in Japanese Unexamined Patent Application Publication No. 2004-31721, for example. A manufacturing method of a conventional semiconductor apparatus disclosed in Japanese Unexamined Patent Application Publication No. 2004-31721 is described hereinafter with reference to FIGS. 10 to 14. FIGS. 10, 11, 13, and 14 are cross-sectional diagrams showing a conventional semiconductor apparatus. FIG. 12 is a plan view showing the conventional semiconductor apparatus of FIG. 11. That is, FIG. 11 is a cross-sectional diagram taken along the line A-A of FIG. 12.
As shown in FIG. 10, a body region 81 is selectively formed over the semiconductor substrate 80. A gate oxidation film 84 and a gate electrode 85 are formed over the semiconductor substrate 80 and the body region 81. Then an interlayer dielectric 86 is formed to cover all the surface of the gate oxidation film 84 and the gate electrode 85.
After that as shown in FIG. 11, a body contact 88 is formed for electrically connecting the body region 81 and the electrode. At this time, a photoresist 90 is formed on the interlayer dielectric 86, and the photoresist 90 is patterned so that the photoresist 90 over the body contact 88 is opened. An etching is performed using the photoresist 90 as a mask, and the interlayer 86 and the gate oxidation film 84 are removed to expose a central part of the body region 81 to form the body contact 88.
Then as shown in FIG. 13, the photoresist 90 on the interlayer dielectric 86 is removed. After that as shown in FIG. 14, a source contact 87 is formed for electrically connecting a source region 82 formed in the body region 81. At this time, an etching is performed over all the surface of the semiconductor apparatus to remove the interlayer dielectric 86 and the gate oxidation film 84 so as to extend the exposed portion of the body region 81. Then the source contact 87 is formed. The semiconductor apparatus is treated with heat, and a body contact region 83 and a source region 82 are formed.
A manufacturing method of a power MOSFET having trench gate structure is disclosed in Japanese Patent Translation Publication No. 2004-522305. The technique disclosed in Japanese Patent Translation Publication No. 2004-522305 etches over all the surface of the semiconductor apparatus as with FIG. 11 to form a source contact.
A relationship between a semiconductor apparatus and bonding force is described in Japanese Patent No. 2756826. As shown in FIG. 15 (the same as the FIG. 1 of Japanese Patent No. 2756826), an electrode over the semiconductor apparatus is bonded with wire in a general power MOSFET. In FIG. 15, a source electrode 81 is formed to contact the source region 82 via a source contact. The source electrode 91 is also used as a bonding pad. An interlayer dielectric 86 may be destroyed in case a bonding wire is bonded to one face of the bonding pad. A thickness of the interlayer dielectric 86 must be thick enough to prevent from being destroyed as at FIG. 14.
Another conventional method of manufacturing a power MOSFET is disclosed in Japanese Patent Translation Publication No. 10-505198. The technique disclosed in Japanese Patent Translation Publication No. 10-505198 implants ion before an interlayer dielectric is formed so that a body contact and source regions are laminated over a surface of a body region. When the interlayer dielectric is etched, source region over the body contact region is removed so as to expose the body contact region. Accordingly with this technique disclosed in Japanese Patent Translation Publication No. 10-505198, a depth of the etching must be deeper in order to form the body contact. Furthermore in Japanese Patent Translation Publication No. 10-505198, the body contact region is formed extending underneath of the gate electrode so that the body contact region overlap with the gate electrode. The under part of the gate electrode is to be a channel region while a MOSFET is operating. In case a high-density body contact region is formed under part of the gate electrode, a threshold of the MOSFET increases, thereby influencing characteristics of the MOSFET.
With the conventional manufacturing method of a semiconductor apparatus illustrated in FIGS. 10 to 14, a source contact is formed by performing an etching over all the surface of the semiconductor apparatus after that photoresist used for forming a body contact is removed. It has now been discovered that with the conventional manufacturing method of a semiconductor apparatus, a thickness of an entire interlayer dielectric decreases along with a removal of the gate oxidation film and the interlayer dielectric which corresponds the area to be the source contact.
In order to prevent the interlayer dielectric from destroying due to its decreased thickness, the interlayer dielectric must be formed thicker in advance. This could require a plurality of forming processes of insulating films, thereby increasing manufacturing cost. Accordingly the thickness of the interlayer dielectric 86 must be thick enough in light of the decrease of it's thickness at the end (such as the film thickness of the interlayer dielectric 86 as at FIG. 14). Further, with considerations of fluctuations in thickness and etching, initial thickness needs to be thick enough to some extent.
Especially in case a thick wire is used to be bonded for a large current, power in bonding becomes enormous, resulting to destroy an interlayer dielectric. In this case, the initial thickness of the interlayer dielectric 86 may need to be for example 2000 nm, which is exceedingly thick. Interlayer dielectric having a thickness of 200 nm cannot be formed in a single process and requires two processes (forming 1000 nm films twice).